1. Technical Field
The present invention relates generally to phase-locked loops (PLLs); more particularly, to PLLs having control of the center frequency of the Voltage Controlled Oscillator (VCO).
2. Discussion of Related Art
In general, increasing PLL oscillation frequency requires a larger VCO gain. To maintain stable loop dynamics, other parameters of the PLL must be adjusted to accommodate the larger VCO gain. Either the charge pump current can be decreased or the loop filter capacitance can be increased and the loop filter resistance correspondingly decreased. If the charge pump current is decreased, the PLL signal-to-noise ratio (SNR) is degraded, causing an increase in jitter. If the loop filter components are altered, the capacitance must increase, requiring larger surface area of the integrated circuit. Therefore, without some alteration to the PLL dynamics or architecture, higher frequency oscillation requires either larger area or higher jitter.
To increase charge pump current and at the same time decrease loop filter capacitance requires a VCO with a much lower gain. A VCO with low gain cannot achieve a wide range of frequencies without some form of auxiliary control, which can center the oscillation frequency or control voltage to a desired value. Normal PLL operation can then be achieved within a small range about the center value.
FIG. 1 shows a prior art PLL. The phase-frequency detector (PFD) 110 detects the difference in phase between two input signals and activates the charge pump 120, which produces a current proportional to the phase difference. The loop filter 140 integrates this current and forces the VCO 150 to change its frequency of oscillation. Feedback divider 130 forces a steady-state condition in which, after the loop has settled, there is no phase difference and the control voltage to the VCO is constant. The feedback divider (M) 130 is used to change the output frequency relative to the input frequency: Fout=MFin. To keep the loop stability constant, any increase in charge pump current requires a corresponding decrease in VCO gain Ko, or a corresponding increase in C1, C2 and decrease in R.
It is recently known that poor charge pump signal-to-noise ratio SNR can be the dominant source of jitter. To reduce jitter, either Ko needs to be decreased or the loop filter capacitors increased to make room for a larger charge pump current. The problem with decreasing Ko is that the frequency range of the VCO will typically be decreased.
There is a type of VCO based on a delay-interpolating ring oscillator where changing Ko does not affect frequency range. See D. W. Boerstler, xe2x80x9cA low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHzxe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 34, no. 4, pp. 513-519, April 1999. However, this type of VCO is incompatible with many commonly used phase mixers. In addition, the voltage compliance of the charge pump will need to be large, thereby increasing charge pump noise. Another drawback to delay-interpolating VCOs is the requirement of a number of gain ranges to span the required frequency range.
Another approach to reducing Ko is to calibrate the center frequency of the VCO. FIG. 2 shows a known implementation of a calibrated VCO. Practically, the PLL acts as a frequency synthesizer to realize Fout=(M/N)Fin. The VCO control voltage is a summation of two paths, one path with high gain through frequency detector 260, counter 270, and digital to-analog converter 280 to set the center frequency during calibration. The second path is with low gain through the traditional loop of PFD 220, charge pump 230, and loop filter 240 to serve as the steady state signal path. Higher gain is employed during calibration only, through the calibration loop. Upon frequency lock or steady state, low gain is employed (through the traditional loop). The input to DAC 280 is held constant after calibration. Thus, Ko is reduced.
Other VCO calibration schemes are shown, for example, in U.S. Pat. Nos. 4,847,569 and 5,382,922. The use of VCO calibration presents several problems, such as during calibration or recalibration, the PLL cannot be used as a clock source. A more complicated design of the frequency detector, a larger voltage compliance on the charge pump output, and a lower noise digital-to-analog converter are needed. Also, errors in miscalibration can occur.
Accordingly, to avoid the above problems, a need exists for a PLL which does not require calibration, having a low gain Ko, and having capability to continuously control the VCO center frequency.
A phase-locked loop (PLL) is provided, having a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO), the PLL comprising: an integrator for integrating an error signal derived from a difference between a reference voltage and an averaged voltage representing an average of voltage output from the loop filter; and a signal combiner at the VCO for combining a control voltage output from the loop filter multiplied by gain Ko, and the integrated voltage from the integrator multiplied by a higher multiple of Ko.
The phase detector, charge pump, loop filter and VCO are interconnected in the loop to cause the average value of the control voltage to be the same value as the reference voltage. The voltage output from the loop filter is applied to a resistor-capacitor divider network and the averaged voltage is taken from any portion of said resistor-capacitor divider network. The PLL is preferably implemented in an integrated circuit.
A phase-locked loop method is also provided, comprising the steps of: frequency synthesizing a signal output from a voltage-controlled oscillator (VCO) by a control voltage input to the VCO; feeding-back the signal to a phase-frequency detector; differencing the frequency of the signal from the frequency of a clock signal; producing a variation of the control voltage output for a loop filter based on the differencing; producing an error signal by comparing a difference between a preset reference voltage and a present portion of the control voltage; integrating the error signal to output integrated voltage; and inputting the integrated voltage to the VCO, wherein a combination of the control voltage and the integrated voltage changes the frequency of the signal output by the VCO.
Preferably, a loop having the control voltage has a gain A and a loop having the integrated voltage has a gain B, wherein B is greater than A. Upon reaching steady state, the error signal is substantially zero.